The digital IF ASIC design consists of two main sections: a front-end which handles high rate sample processing and a back-end which is a collection of signal processing blocks for low-rate baseband processing. The focus here is on the front-end section of the digital IF where the high sampling rate eliminates the possibility of re-targeting with a software-based design.

The digital IF ASIC operates in either receive or transmit mode based on configuration data provided from a support processor. The signal-path routing in the front-end is largely fixed and consists of the following functions:

• Input (analog to digital converter) Stage

• Output (digital to analog converter) Stage

• Gain Scale Control

• Wideband Mixer

• Wideband Numerically Controlled Oscillator (NCO)

• Wideband Interpolator

• Cascaded Integrate and Comb (CIC) Filter

• Compensating Finite Impulse Response (CFIR) Filter

• Programmable Finite Impulse Response (PFIR) Filter

These signal-processing blocks are used both in receive and transmit modes with the overall signal flow reversed between the two modes (see Figures).

The symbol rate of the front-end decreases from the input stage to the PFIR filter (back-end connection point) for receive and increases from the PFIR filter to the output stage for transmit. The analog interface stages operate at a 960-KHz sample rate. The device converts between a real and complex, in-phase (I) and quadrature (Q), signal. Decimation and interpolation factors within the front-end permit a wide range of back-end sample rates. An internally generated high rate processing clock allows symbol processing at rates higher than the analog sampling rate.

The programmable logic technology chosen for the ASIC re-targeting effort was the Altera (San Jose, CA) APEX 20KE family. The technology offers a high level of integration of programmable logic and embedded memory. This logic family also provides clock management circuitry that includes on-chip digital phase-locked loops (PLLs). Additionally, the Altera development environment supports a large suite of intellectual property (IP) megafunctions for signal processing applications.

The prototype hardware used to test the digital IF PLD consists of a daughterboard containing an EP20K400E PLD with an adapter socket, which maps to the footprint of the ASIC package. A production radio signal processing module, with ASIC removed, serves as the host for this prototype board. The daughterboard also has two 14-bit DAC devices which enable monitoring of a complex signal. Monitoring is done in both the frequency and time domain.

The digital IF PLD uses a high rate processing clock to drive hardware blocks at a sufficient rate to meet the sample throughput requirement. The input (receive) and output (transmit) stage sample streams operate at 960K samples per second. The Altera PLD, utilizing an on-chip PLL, internally generates a processing clock operating at 20 times the input sample rate. Using an external 4.8-MHz system reference, which is phase locked to the input sample clock, an on-chip PLL is able to synthesize a 19.2-MHz processing clock. The system architecture uses a clock with enable topology, which distributes a high rate system clock to all control and storage circuits. Control logic and state machines generate enable signals for these circuits. An enable signal must be active for the clock to affect a circuit's output.

The input and output sample clocks synchronize control logic in the PLD. Transitions on the sample clocks determine when an input or output sample is read from or written to the sampling device (ADC or DAC). In receive mode, control for the first four blocks (input, gain-scale control, wideband mixer, and interpolator) is performed in the initial synchronization logic. These blocks all run at the same symbol rate. Control logic within the remaining blocks (CIC, CFIR, PFIR) provide enable signals for the next block in the signal path. These three blocks apply filtering and rate conversion to the signal. Decimation (dropping samples from a higher to a lower rate stage in a periodic manner) occurs in receive mode. Interpolation (a periodic insertion of a 'zero' sample into a higher rate stage when a lower rate stage has no actual sample to supply) occurs in transmit.

The digital IF PLD front-end receive path processes an IF signal centered at 240 KHz (see Figure 1). The information bandwidth of the signal varies depending on the user configuration of the device. Bandwidths vary from 3 KHz for narrow band (HF) signals, to 25 KHz for wider bandwidth (VHF and UHF) signals. The input stage block applies format conversion (offset binary to two's complement) of the ADC sample. The actual sampling device is 12 bits wide; the remaining four bits are output by a gain control circuit which supplies a gain scale factor to the digital IF. The gain scale control block applies this four bit 'exponent' to the input sample 'mantissa' to produce a higher resolution input sample (16 bits).

The output of the gain scale control block is fed to the wideband mixer block. The function of this block is to mix the input IF signal with a local oscillator (LO) frequency centered at 240 KHz. The IF center frequency is produced within the digital IF by a numerically controlled oscillator (NCO), part of the wideband NCO block. This block is generated using the Altera NCO compiler. The block takes as input a phase increment and clock input and produces a complex (sine and cosine) LO output. The angular precision (input) and magnitude precision (output) parameters are all programmable within the NCO compiler as well as the synthesis algorithm used. For low-resolution parameters, a look-up table based algorithm can be selected.

For the high-resolution parameters used in this design, a coordinate rotation digital computer (CORDIC) algorithm is selected due to the large memory requirements imposed by the look-up table algorithm. The CORDIC algorithm is based on the idea of complex phasor rotation by multiplication of the phase angle by successively smaller constants. The multiplications are by powers of two only. Therefore, the algorithm can be implemented efficiently by a series of binary shifts and additions. For the digital IF design, a 28-bit phase increment is used which provides a frequency resolution of 960K/228. The output frequency word resolution is 20 bits.

The NCO output frequency is positioned at the center of the information band of the received signal.

For narrowband signals, this is typically a few kilohertz away from the IF center of 240 KHz. The NCO complex frequency is mixed with the IF signal to produce a complex output with components at spectral bands equal to the sum and difference of the input frequencies. Mathematically, the mix operation consists of a pair of multiply operations followed by addition and subtraction operations governed by the basic equation for a complex frequency mix:

NCO: I + jQ
Input Signal: A + jB
Output spectrum = AI - QB + j(AQ + IB)

In this case, the input signal is real only, therefore the 'B' part of the input is zero, which reduces the actual computation to:

Output spectrum = AI + j(AQ)

The wideband mixer block produces this complex output, which amounts to only half of the computations required for a full mix operation. The processing clock, running at 20 times the input rate, drives a control block in the mixer which directs the multiply operations at early and late cycles in the sample period, time-sharing the multiplier hardware. The output stream is clipped and rounded to an 18-bit result and registered to produce a stable value for the next stage. The intermediate products produced by the multiplier are up-shifted to remove any sign-bit growth. At this point in the signal path, a complex signal (real and imaginary) exists. Each path is treated as a separate hardware instance in the digital IF.

The function of the wideband interpolator block is to insert zeroes into the sample stream in order to raise the effective sample rate of the stream and negate the effects of fixed decimation further downstream in the processing. Interpolation factors (none, two, and four) are user programmable based on the detection mode of the system.

The cascaded integrate and comb (CIC) filter block consists of four elements: an integrator, a decimator, an interpolator, and a differentiator. CIC filters are often used as economical replacements for conventional FIR filters because they require no multipliers (which allows them to operate at high sample rates) and can provide large decimation (rate reduction) factors (see Figure 2). More complex filter blocks such as FIR filters can then further process the output of a CIC filter. Hogenauer discusses the basic topology of CIC filters (ref. 1).

The integrate section of the CIC filter block consists of five cascaded digital integrators. The integrators operate at the input sample rate of 960 KHz. Its output drives a decimator block that, in turn, drives a differentiator block at a lower rate. In a typical case, the CIC filter will reduce the sampling rate of a narrowband signal from 960 KHz to 32 KHz (decimation factor of 30). The differentiator section consists of five cascaded digital subtractors. This type of filter is also referred to as a comb filter because its output spectrum resembles the teeth of a comb. The filter notches occur at periodic frequency intervals determined by the number of stages of the filter.

Having sufficiently wide register widths for symbol processing within each block is critical; overflow in the integrator or underflow in the differentiator can cause the system to become permanently unstable.

In this implementation, the five stages of the integrator section vary in width from 78 to 65 bits. The differentiator section registers are all 24 bits wide. The output resolution of the CIC filter block is rounded and clipped to 18 bits. A downshift block at the input of the integrator prevents overflow due to bit growth. The aliasing attenuation of the filter is greater than 90 dB. Its usable bandwidth is 0.2 relative to its own output sample rate.

The passband of the CIC filter is not flat, but is characterized by sin(x)/x shape. To compensate for this roll-off effect, the signal is passed through a compensating FIR filter. The CFIR filter block is a 32-tap filter with fixed coefficients that has a passband shape which is inverse to the CIC filter passband. This block has a fixed decimation rate of two and it limits the CIC filter block output bandwidth so that in-band aliasing distortion is suppressed by at least 90 dB. Stopband attenuation of the CFIR filter is 93 dB. The combined passband ripple of the CIC and CFIR filters is 0.1 dB. Like the CIC filter, the output of the CFIR filter block is rounded and clipped to 18 bits. The Altera FIR filter compiler supplies the core of this block. The compiler 'wizard' interface allows the designer to specify many parameters that control the filter design.

The lowest rate stage in the front-end section is the programmable FIR filter block. The PFIR filter block provides symmetrical variable length FIR filters up to 128 taps. The filter coefficients are stored in memory within the device. This block's primary responsibility is to provide a frequency selective, band-limited signal to a back-end system or DSP; it does not use the FIR compiler, but is based on a propriety design supplied by Altera. This block also decimates the signal sample rate by two. Therefore, a 32-KHz sample rate signal at the CIC filter output will reduce to an 8-KHz sample rate at the output of the PFIR filter block. This is a typical sample rate for many voice-band signals. The output resolution of the PFIR filter block is rounded and clipped to 16 bits.

The front-end transmit path in terms of signal flow, is a reversal of the receive path of the digital IF PLD (see Figure 3). In terms of hardware resources, the transmit path largely reuses the receive path. In the CIC filter block, samples are first processed by the comb (differentiator) section, which then feeds the integrate section through a programmable interpolator. The interpolator will increase the sample rate of the comb output by inserting zeroes at every high-rate sample period when no low rate sample is available. When interpolation is performed, a multiplexer routing the signal path is switched to channel a set of zero values to all bits on the signal bus.

The Altera APEX 20K family includes a range of devices, which provide from 1,200 to 52,000 logic elements (LEs). The device used in this design, the EP20K400E, contains 16,640 LEs. In addition, the device contains 212,992 embedded system block (ESB) bits that are used to implement memory functions. The digital IF design consumed 5,730 LE's and 16,992 ESB bits.

One of the goals of re-targeting the digital IF ASIC in a programmable logic device is to minimize the amount of logic required to implement the design. Reducing the amount of logic in the design decreases both the cost and power consumption of the system (unless the logic reduction is obtained by increasing the clocking rate of the remaining logic, which may increase the total power consumption of the design).

The main opportunity for logic reduction is the reuse of the logic elements for receive and transmit modes of the device. Since the modes reuse the same basic building blocks of the design, this technique essentially reduces the required logic by half at the expense of some multiplexing logic for selecting receive and transmit data paths. Another optimization technique inherent in the NCO compiler is the use of the CORDIC algorithm for implementing the wideband NCO. In fact, this design would not have been realizable using a look-up table based NCO. The memory requirements for a 28-bit phase increment input for the NCO would have required an external memory array for storage even with a much denser APEX device. Likewise, choosing the serial structure option in the FIR compiler reduces the logic requirements of the CFIR filter block by an amount proportional to the input data width (18 bits) of this block.

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